(a) Field of the Invention
The present invention relates to a method for forming a transistor, and more particularly, to a method for forming a transistor with a reduced channel length.
(b) Description of the Related Art
Generally, a transistor is formed with a gate oxide layer and a gate polysilicon layer which are sequentially accumulated thereon. Typically, a source/drain region is formed at both sidewalls of the gate polysilicon layer. Hereinafter, a conventional method of forming a transistor will be described.
FIG. 1 to FIG. 3 are cross-sectional views showing a conventional method for forming a transistor.
Referring to FIG. 1 and FIG. 2, a gate oxide layer 12 and a gate polysilicon layer 14 are formed on a silicon substrate 10. A gate polysilicon layer pattern 14a is formed by patterning the gate polysilicon layer 14. A gate oxide layer pattern 12a is formed by patterning the gate oxide layer 12. Subsequently, a low energy ion implantation region 16 is formed to be aligned with both sides of the gate polysilicon layer pattern 14a. A halo ion implantation region 18 is formed below the low energy ion implantation region 16.
Referring to FIG. 3, a gate spacer 21 is formed at both sidewalls of the gate polysilicon layer pattern 14a. Subsequently, a high energy ion implantation region 22 is formed by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern 14a and gate spacer 21. Consequently, a source/drain region is composed of the low energy ion implantation region 16, pocket ion implantation region 18, and high energy ion implantation region 22.
However, according to a conventional method for forming a transistor, chlorine based gases, such as Cl2, BCl3, etc., are used in etching a gate polysilicon layer so as to prevent damage on lateral sides of the gate polysilicon layer.
Accordingly, as shown in FIG. 2, a polymer 20 is formed more thickly in a lower part of the gate polysilicon layer pattern 14a than in an upper part thereof. Consequently, as shown in FIG. 3, the gate polysilicon layer pattern 14a has a positive etch profile 24. Such a positive etch profile increases an effective channel length.
In addition, when fluorine based gases, such as SF6, CF4, C2F8, CHF3, etc., are used for an isotropic etching process to prevent a channel length increase, it is possible to induce other problems, such as a decrease of a pattern size or deterioration of a pattern opening in a place where the height difference is great.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form prior art already known in this country to a person of ordinary skill in the art.